Optimum design of reliable IC power networks having general graph topologies
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Power and ground network topology optimization for cell based VLSIs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Design and analysis of power distribution networks in PowerPC microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The construction of minimal area power and ground nets for VLSI circuits
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Design of robust global power and ground networks
Proceedings of the 2001 international symposium on Physical design
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Area minimization of power distribution network using efficient nonlinear programming techniques
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Inductive properties of high-performance power distribution grids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Floorplan and power/ground network co-synthesis for fast design convergence
Proceedings of the 2006 international symposium on Physical design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the Conference on Design, Automation and Test in Europe
IR-drop in on-chip power distribution networks of ICs with nonuniform power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Robust power distribution within available routing area resources is critical to chip performance and reliability. In this paper, we propose a novel and efficient method for optimizing worst-case static IR-drop in hierarchical, uniform power distribution networks. Our results can be used for planning of hierarchical power distribution in early design stages, so that for a fixed total routing area the worst-case IR-drop on the power mesh is minimal, or for a given IR-drop tolerance the power mesh achieves the IR-drop specification with minimal routing area. Our contributions are as follows. (1) We derive a closed-form approximation for the worst-case IR-drop on a single-level power mesh. The formula shows that for a given total routing area, the worst-case IR-drop increases logarithmically with the number of metal lines on the mesh. (2) Based on the previous analysis and empirical studies, we propose a model for the worst-case static IR-drop on a two-level power mesh, and obtain an accurate empirical expression. (3) Using this expression, we present a novel approach to optimize the two-level mesh topology. (4) We extend our study to three-level power meshes, and find that a third, middle-level mesh helps to reduce IR-drop by only a relatively small extent (about 5%, according to our experiments).