Optimum design of reliable IC power networks having general graph topologies
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Power and ground network topology optimization for cell based VLSIs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Congestion-driven codesign of power and signal networks
Proceedings of the 39th annual Design Automation Conference
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
Topology optimization of structured power/ground networks
Proceedings of the 2004 international symposium on Physical design
Optimal placement of power supply pads and pins
Proceedings of the 41st annual Design Automation Conference
Optimal planning for mesh-based power distribution
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A fast algorithm for power grid design
Proceedings of the 2005 international symposium on Physical design
VLSI on-chip power/ground network optimization considering decap leakage currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Large scale P/G grid transient simulation using hierarchical relaxed approach
Integration, the VLSI Journal
Vertical via design techniques for multi-layered P/G networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Optimization of via distribution and stacked via in multi-layered P/G networks
Integration, the VLSI Journal
Proceedings of the Conference on Design, Automation and Test in Europe
Smart non-default routing for clock power reduction
Proceedings of the 50th Annual Design Automation Conference
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This paper deals with area minimization of power distribution network for VLSIs. A new algorithm based on efficient nonlinear programming techniques is presented to solve this problem. The experiment results prove that this algorithm has achieved the objects that minimize the area of power/ground networks with higher speed.