Power and ground network topology optimization for cell based VLSIs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multi-pad power/ground network design for uniform distribution of ground bounce
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multi-pads, single layer power net routing in VLSI circuits
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Hierarchical analysis of power distribution networks
Proceedings of the 37th Annual Design Automation Conference
Fast power/ground network optimization based on equivalent circuit modeling
Proceedings of the 38th annual Design Automation Conference
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Area minimization of power distribution network using efficient nonlinear programming techniques
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On-chip power supply network optimization using multigrid-based technique
Proceedings of the 40th annual Design Automation Conference
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Topology optimization of structured power/ground networks
Proceedings of the 2004 international symposium on Physical design
Optimal placement of power supply pads and pins
Proceedings of the 41st annual Design Automation Conference
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Placement optimization of power supply pads based on locality
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an iterative procedure, the chip area is recursively bipartitioned, and the wire pitches and the wire widths of the power grid in the partitions are repeatedly adjusted to meet the voltage drop and current density specifications. By using the macromodels of the power grid constructed in the previous levels of partitioning, the scheme ensures that a small global power grid system is simulated in each iteration. A post-processing step at the end of the optimization is employed to maximize the alignment of wires in adjacent partitions. The effectiveness of the scheme is demonstrated by designing various power grids with real circuit parameters and realistic input current values. The proposed algorithm is able to design power grids comprising thousands of wires and more than a million electrical nodes in about 7-16 minutes. The proposed design scheme as compared to a multigrid-based power grid design scheme saves about 7%-12% of wire area.