Automatic sizing of power/ground (P/G) networks in VLSI
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Optimum design of reliable IC power networks having general graph topologies
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Fast analysis and optimization of power/ground networks
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Challenges in power-ground integrity
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Topology optimization of structured power/ground networks
Proceedings of the 2004 international symposium on Physical design
Efficient power/ground network analysis for power integrity-driven design methodology
Proceedings of the 41st annual Design Automation Conference
A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Power/Ground Mesh Area Optimization Using Multigrid-Based Technique
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A fast algorithm for power grid design
Proceedings of the 2005 international symposium on Physical design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Relaxed hierarchical power/ground grid analysis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Journal of Computer Science and Technology
Electromigration and voltage drop aware power grid optimization for power gated ICs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Large scale P/G grid transient simulation using hierarchical relaxed approach
Integration, the VLSI Journal
Analysis and optimization of power-gated ICs with multiple power gating configurations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Effective decap insertion in area-array SoC floorplan design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs
Proceedings of the 2009 International Conference on Computer-Aided Design
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Reliability analysis and optimization of power-gated ICs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an efficient algorithm for optimizing the area of power or ground networks in integrated circuits subject to the reliability constraints. Instead of solving the original power/ground networks extracted from circuit layouts as previous methods did, the new method first builds the equivalent models for many series resistors in the original networks, then the sequence of linear programming method [9] is used to solve the simplified networks. The solutions of the original networks then are back solved from the optimized, simplified networks. The new algorithm simply exploits the regularities in the power/ground networks. Experimental results show that the complexities of simplified networks are typically significantly smaller than that of the original circuits, which renders the new algorithm extremely fast. For instance, power/ground networks with more than one million branches can be sized in a few minutes on modern SUN workstations.