Power and ground network topology optimization for cell based VLSIs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Single-layer fanout routing and routability analysis for Ball Grid Arrays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Fast power/ground network optimization based on equivalent circuit modeling
Proceedings of the 38th annual Design Automation Conference
Pin assignment on a printed circuit board
DAC '78 Proceedings of the 15th Design Automation Conference
Pin assignment in automated printed circuit board design
DAC '72 Proceedings of the 9th Design Automation Workshop
P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Physical Design for 3D System on Package
IEEE Design & Test
VLSI on-chip power/ground network optimization considering decap leakage currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast algorithms for IR drop analysis in large power grid
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
The importance of adopting a package-aware chip design flow
Proceedings of the 43rd annual Design Automation Conference
Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Congestion-aware topology optimization of structured power/ground networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing by iterative improvements for two-layer ball grid array packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IR-drop in on-chip power distribution networks of ICs with nonuniform power consumption
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs
Integration, the VLSI Journal
| Hi-index | 0.00 |
Due to increasing complexity of design interactions between the chip, package and PCB, it is essential to consider them at the same time. Specifically the finger/pad locations affect the performance of the chip and the package significantly. In this paper, we have developed techniques in chip-package codesign to decide the locations of fingers/pads for package routability and signal integrity concerns in chip core design. Our finger/pad assignment is a two-step method: first we optimize the wire congestion problem in package routing, and then we try to minimize the IR-drop violation with finger/pad solution refinement. The experimental results are encouraging. Compared with the randomly optimized methods, our approaches reduce in average 42% and 68% of the maximum density in package and 10.61% of IR-drop for test circuits.