Single-layer fanout routing and routability analysis for Ball Grid Arrays
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Pin assignment on a printed circuit board
DAC '78 Proceedings of the 15th Design Automation Conference
Pin assignment in automated printed circuit board design
DAC '72 Proceedings of the 9th Design Automation Workshop
P/G Pad Placement Optimization: Problem Forumulation for Best IR Drop
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Physical Design for 3D System on Package
IEEE Design & Test
VLSI on-chip power/ground network optimization considering decap leakage currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast algorithms for IR drop analysis in large power grid
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Efficient Second-Order Iterative Methods for IR Drop Analysis in Power Grid
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design
Proceedings of the Conference on Design, Automation and Test in Europe
An Approach to Topological Pin Assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Congestion-aware topology optimization of structured power/ground networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global routing by iterative improvements for two-layer ball grid array packages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Due to the increasing complexity of the design interactions between the chip and package, it is necessary to consider them at the same time. In order to simultaneously handle chip and package performances, co-design of chip and package is a widely adopted solution, particularly because the finger/pad locations significantly affect IR-drop of the core and the package routing. In this paper, we develop chip-package co-design techniques to determine the locations of the fingers/pads for package routability and signal integrity concerns in IC designs, this method can be used in the 2-D and stacking IC design. Our finger/pad assignment is a two-step method: we first solve the wire congestion problem in package routing, and then try to minimize the IR-drop violation and the length of the bonding wires under a compact IR-drop model. The experimental results are encouraging. Compared with the randomly optimized method, on average, our approaches reduce the maximum package density by 42% and 68% for both technologies, IR-drop by 10.61% and 4.58%; and the bonding wires is reduced by 15.66% if we use stacking chips.