Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A correct network flow model for escape routing
Proceedings of the 46th Annual Design Automation Conference
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design
Proceedings of the Conference on Design, Automation and Test in Europe
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
On the escape routing of differential pairs
Proceedings of the International Conference on Computer-Aided Design
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs
Integration, the VLSI Journal
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In current very large scale integration (VLSI) circuits, there can be hundreds of required I/O pins. Ball grid array (BGA) packaging is commonly used to realize the huge number of connections between VLSI chips and printed circuit boards (PCBs). In this paper, the authors propose a global-routing method by iterative improvements for two-layer BGA packages. In their routing model, the global routing for each net is uniquely determined by a via assignment. The proposed global-routing method begins with an initial feasible via assignment and incrementally improves the via assignment to minimize the maximum wire congestion and the total wire length. In each iteration, a via assignment is improved by exchanging two adjacent vias or by moving vias one by one to their adjacent grids. The algorithm efficiently generates better global routes than initial routes with respect to wire congestion and total wire length.