Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design
Proceedings of the Conference on Design, Automation and Test in Europe
Parallel and scalable transient simulator for power grids via waveform relaxation (PTS-PWR)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient algorithms for fast IR drop analysis exploiting locality
Integration, the VLSI Journal
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs
Integration, the VLSI Journal
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Due to the extremely large sizes of power grids, IR drop analysis has become a computationally challenging problem both in terms of runtime and memory usage. It has been shown in [5] that first-order iterative algorithms based on node-by-node and row-by-row traversals of the power grid have both accuracy and runtime advantages over the well-known Random-Walk method. In this paper, we propose second-order iterative algorithms that can significantly reduce the runtime. The new algorithms are extremely fast, and we prove that they guarantee converge to the exact solutions. Experimental results show that our algorithms outperform the Random-Walk algorithm in [2] and algorithms in [5]. For a 25-million node problem, while the Random-Walk algorithm takes 2 days with maximum error of 6.1 mV, the fastest algorithm in [5] takes 50 minutes, and our second-order row-based algorithm takes 32 minutes to get an exact solution. Moreover, we can get a solution with maximum error 2 mV in 10 minutes.