Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Signal skew aware floorplanning and bumper signal assignment technique for flip-chip
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
B-escape: a simultaneous escape routing algorithm based on boundary routing
Proceedings of the 19th international symposium on Physical design
Recent research development in PCB layout
Proceedings of the International Conference on Computer-Aided Design
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs
Integration, the VLSI Journal
| Hi-index | 0.03 |
Shrinking transistor sizes, increasing circuit complexities, and high clock frequencies bring new board-routing challenges that cannot be handled effectively by traditional routing algorithms. Many high-end designs in the industry today require manual routing efforts, which increases the design-cycle times considerably. In this paper, we propose an escape-routing algorithm to route nets within multiple dense components simultaneously so that the number of crossings in the intermediate area is minimized. We also show how to handle high-speed-design constraints within the framework of this algorithm. Experimental comparisons with a recently proposed algorithm show that our algorithm reduces the via requirements of industrial test cases on average by 39%.