Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
B*-Trees: a new representation for non-slicing floorplans
Proceedings of the 37th Annual Design Automation Conference
Timing-driven placement based on partitioning with dynamic cut-net control
Proceedings of the 37th Annual Design Automation Conference
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A global routing method for 2-layer ball grid array packages
Proceedings of the 2005 international symposium on Physical design
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
Constraint driven I/O planning and placement for chip-package co-design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Simultaneous block and I/O buffer floorplanning for flip-chip design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
The importance of adopting a package-aware chip design flow
Proceedings of the 43rd annual Design Automation Conference
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Flip-chip is a solution for designs requiring more I/O pins and higher speed. However, the higher speed demand also brings the issue of signal skew. In this paper, we propose a new 3-stage design layout methodology for flip-chip considering signal skew. Firstly, we produce an initial bumper signal assignment, and then solve the flip-chip floorplanning problem using a partitioning-based technique to spread the modules across the flip-chip as the distribution of its bumpers. With an anchoring and relocation strategy, we can effectively place I/O buffers at desirable locations. Finally, we further reduce signal skew and monotonic routing density by refining the bumper signal assignment. Experimental results show that signal skew of traditional floorplanners range from 4% to 280% higher than ours. And the total wirelength of other floorplanners is as much as 100% higher than ours. Moreover, our signal refinement method can further decrease monotonic routing density by up to 8% and signal skew by up to 11%.