Power distribution techniques for dual VDD circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Vertical via design techniques for multi-layered P/G networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Effective decap insertion in area-array SoC floorplan design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimization of via distribution and stacked via in multi-layered P/G networks
Integration, the VLSI Journal
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design
Proceedings of the Conference on Design, Automation and Test in Europe
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs
Integration, the VLSI Journal
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This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the power grid chip area into rectangular subgrids or tiles. Treating the entire power grid to be composed of many tiles connected to each other enables the use of a hierarchical circuit analysis approach to identify the tiles containing the nodes having the greatest drops. Starting from an initial configuration with an equal number of wires in each of the rectangular tiles, wires are added in the tiles using an iterative sensitivity based optimizer. A novel and efficient table lookup scheme is employed to provide gradient information to the optimizer. Incorporating a congestion penalty term in the cost function ensures that regularity in the grid structure does not aggravate congestion. Experimental results on test circuits of practical chip sizes show that the proposed P/G network topology, after optimization, saves 12%-23% of the chip-wiring area over other commonly used topologies.