IR-drop management in FPGAs

Authors:
Akhilesh Kumar;Mohab Anis
Affiliations:
Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada;Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Year:
2010

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Abstract

This paper presents novel computer-aided design (CAD) techniques for mitigating IR-drops in field-programmable gate arrays (FPGAs). The proposed placement and routing relies on reducing the switching activities in local regions in the FPGA fabric to improve the profile of the supply voltage distribution. The proposed techniques reduce IR-drops and the variance of the supply voltage distribution across all the nodes in the power grid network. The proposed CAD techniques are efficient as they do not require solving the power grid model at every placement and routing iteration. A reduction of up to 53% in maximum IR-drop and up to 66% reduction in standard deviation of Vdd is obtained from the design techniques proposed in this paper with an average impact of 3% on circuit delay.