IR-drop management CAD techniques in FPGAs for power grid reliability

Authors:
Akhilesh Kumar;Mohab Anis
Affiliations:
Dept. of ECE, University of Waterloo, ON, Canada N2L3G1;Dept. of ECE, University of Waterloo, ON, Canada N2L3G1
Venue:
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Year:
2009

Citing 0
Cited 2

IR-drop management in FPGAs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

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Abstract

The design of power grid network is critical in scaled technologies for reliable operation of a circuit. This paper presents novel CAD techniques for mitigating IR-drops in FPGAs. Placement and routing techniques are developed in the paper for improving the voltage profile of the power grid network. The proposed techniques not only improve the minimum voltage at any node in the FPGA power grid, but also reduces the variance of the supply voltage distribution across all the nodes in the power grid. An improvement of up to 7% in the minimum Vdd and up to 66% reduction in standard deviation of Vdd is obtained from the design technique proposed in this paper.