A novel technique for incremental analysis of on-chip power distribution networks
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Incremental and on-demand random walk for iterative power distribution network analysis
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Locality-driven parallel power grid optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Line width optimization for interdigitated power/ground networks
Proceedings of the 20th symposium on Great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Multi-layer interdigitated power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an efficient heuristic algorithm, which employs successive partitioning and grid-refinement scheme, for designing the power distribution network of a chip. In an iterative procedure, the chip area is recursively bipartitioned, and the wire pitches and the wire widths of the power grid in the partitions are repeatedly adjusted to meet the voltage drop and current-density specifications. By using the macromodels of the power grid constructed in the previous levels of partitioning, the scheme ensures that a small global power grid system is simulated in each iteration. The idea is based on the notion that due to the locality properties of the power grid, the effects of distant nodes and sources can be modeled more coarsely than the nearby elements, and include practical methods that enhance the convergence of the iterative conjugate-gradient-based solution engine that is used in each step. Finally, a postprocessing step at the end of the optimization is employed to maximize the alignment of wires in adjacent partitions. The effectiveness of the scheme is demonstrated by designing various power grids with real circuit parameters and realistic input current values. The proposed algorithm is able to design power grids comprising thousands of wires and more than a million electrical nodes in about 6 to 14 min. When compared to a multigrid-based power grid design scheme, it is found to save about 5% to 10% of wire area, and on an average is 12% faster.