Analog Integrated Circuits and Signal Processing
Simultaneous switching noise in on-chip CMOS power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of IR-Drop Scaling with Implications for Deep Submicron P/G Network Designs
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Scaling trends of on-chip power distribution noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Power Distribution Networks with On-Chip Decoupling Capacitors
Power Distribution Networks with On-Chip Decoupling Capacitors
Inductance model of interdigitated power and ground distribution networks
IEEE Transactions on Circuits and Systems II: Express Briefs
Inductive properties of high-performance power distribution grids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip power-supply network optimization using multigrid-based technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Partition-based algorithm for power grid design using locality
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Higher operating frequencies have increased the importance of inductance in power and ground networks. The effective inductance of the power and ground network can be reduced with an interdigitated structure. A closed-form solution for determining the optimal power and ground wire width is described, producing the minimum impedance within an interdigitated structure. The optimal wire width is determined under different physical network dimensions and signal frequencies, suggesting useful trends for interdigitated power and ground networks. In addition, a closed-form expression for the optimal wire width is determined that minimizes the voltage drop over a single metal layer of an interdigitated power/ground network.