Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Power Distribution Networks with On-Chip Decoupling Capacitors
Power Distribution Networks with On-Chip Decoupling Capacitors
Inductive properties of high-performance power distribution grids
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Line width optimization for interdigitated power/ground networks
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Multi-layer interdigitated power distribution networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
A closed-form expression is presented in this brief to accurately estimate the effective inductance of a single layer within an interdigitated power and ground (P/G) distribution network. Due to the large number of P/G lines in these networks, excessive time is required to calculate the inductance using 3-D simulation tools. The proposed expression is favorably compared with previous models and FastHenry, exhibiting accuracy and computational efficiency. The inductance of a single layer within an interdigitated P/G distribution network is bounded for any number of lines. The error of the proposed expression rapidly decreases with an increasing number of pairs within the network. The upper bound for the error of the proposed model is also determined.