Matrix computations (3rd ed.)
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accurate power grid analysis with behavioral transistor network modeling
Proceedings of the 2007 international symposium on Physical design
Robust test generation for power supply noise induced path delay faults
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Generating Worst-Case Stimuli for Accurate Power Grid Analysis
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Transition-aware decoupling-capacitor allocation in power noise reduction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Context-sensitive static transistor-level IR analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Generating realistic stimuli for accurate power grid analysis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A parallel direct solver for the simulation of large-scale power/ground networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design
Proceedings of the Conference on Design, Automation and Test in Europe
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A fast approximation technique for power grid analysis
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Parallel and scalable transient simulator for power grids via waveform relaxation (PTS-PWR)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fast algorithms for IR voltage drop analysis exploiting locality
Proceedings of the 48th Design Automation Conference
Fast static analysis of power grids: algorithms and implementations
Proceedings of the International Conference on Computer-Aided Design
Power grid analysis with hierarchical support graphs
Proceedings of the International Conference on Computer-Aided Design
Efficient algorithms for fast IR drop analysis exploiting locality
Integration, the VLSI Journal
Deterministic random walk preconditioning for power grid analysis
Proceedings of the International Conference on Computer-Aided Design
Voltage propagation method for 3-D power grid analysis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs
Integration, the VLSI Journal
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Journal of Electronic Testing: Theory and Applications
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Due to the extremely large size of power grids, IR drop analysis has become a computationally challenging problem both in terms of runtime and memory usage. Although IR drop analysis can be naturally formulated as the problem of solving a linear system, the system is too large to be solved by existing linear solvers. In this paper, we present two iterative algorithms based on node-by-node traversals and row-by-row traversals of the power grid, respectively. Our algorithms are extremely fast and guarantee convergence to the exact solutions. In fact, they can be considered as efficient implementations of the classical successive over relaxation iterative method for solving linear systems. Our methods take full advantage of the special structure of the power grid. Experimental results show that our algorithms out-perform the random-walk-based algorithm which is the best known method today. For a 16-million node problem, our row-based algorithm took 26.47 minutes while the random-walk-based algorithm took 19.6 hours. Our row-based algorithm produced an exact solution while the random walk produced a solution with maximum error of 5.7 mV.