Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power considerations in the design of the Alpha 21264 microprocessor
DAC '98 Proceedings of the 35th annual Design Automation Conference
Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
A static pattern-independent technique for power grid voltage integrity verification
Proceedings of the 40th annual Design Automation Conference
Power grid reduction based on algebraic multigrid principles
Proceedings of the 40th annual Design Automation Conference
Fast algorithms for IR drop analysis in large power grid
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Incremental partitioning-based vectorless power grid verification
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Fast Placement Optimization of Power Supply Pads
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Hierarchical analysis of power distribution networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Early-stage power grid analysis for uncertain working modes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With advances in semiconductor process technology, chip power density has dramatically increased, making power grid integrity a critical concern at all stages of the design process. Given the inherent difficulty of capturing worst-case IR drops for all logic gates with dynamic vectors, a static flow is essential for verifying grid integrity on complex chip designs, especially microprocessors. A novel static transistor-level IR drop analysis flow which significantly reduces the conservatism of other static flows is presented. The key feature of this flow is a fast NAND decision diagram (NDD) algorithm, a lightweight variant of a boolean decision diagram (BDD) with the capacity to effectively process device transition exclusions in a per logical-device, context-sensitive fashion, thereby radically reducing the conservatism typical of static analysis.