Accurate power grid analysis with behavioral transistor network modeling
Proceedings of the 2007 international symposium on Physical design
Context-sensitive static transistor-level IR analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
More realistic power grid verification based on hierarchical current and power constraints
Proceedings of the 2011 international symposium on Physical design
Efficient incremental analysis of on-chip power grid via sparse approximation
Proceedings of the 48th Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
Power grid analysis and verification considering temperature variations
Microelectronics Journal
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High-performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance of the power delivery system requires knowledge of the current drawn by the functional blocks that comprise a typical hierarchical design. However, current designs are of such complexity that it is difficult for a designer to determine what a realistic worst-case switching pattern for the various blocks would be in order to maximize noise at a specific location. This paper uses information about the power dissipation of a chip to derive an upper bound on the worst-case voltage drop at an early stage of design. An exact integer linear programming (ILP) method is first developed, followed by an effective heuristic to speed up the exact method. A circuit of 43 K nodes is analyzed within 70 s, and the worst-case scenarios found correlate well with the results from an ILP solver.