Vector generation for power supply noise estimation and verification of deep submicron designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Static Verification of Test Vectors for IR Drop Failure
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fast flip-chip power grid analysis via locality and grid shells
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast algorithms for IR drop analysis in large power grid
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Power grid physics and implications for CAD
Proceedings of the 43rd annual Design Automation Conference
Defect Simulation Methodology for iDDT Testing
Journal of Electronic Testing: Theory and Applications
Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits
MTV '06 Proceedings of the Seventh International Workshop on Microprocessor Test and Verification
Supply Voltage Noise Aware ATPG for Transition Delay Faults
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Proceedings of the conference on Design, automation and test in Europe
Effect of IR-Drop on Path Delay Testing Using Statistical Analysis
ATS '07 Proceedings of the 16th Asian Test Symposium
Layout-aware, IR-drop tolerant transition fault pattern generation
Proceedings of the conference on Design, automation and test in Europe
Journal of Electronic Testing: Theory and Applications
Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
A multigrid-like technique for power grid analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scalable dynamic technique for accurately predicting power-supply noise and path delay
VTS '13 Proceedings of the 2013 IEEE 31st VLSI Test Symposium (VTS)
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Power-supply noise is one of the major contributing factor for yield loss in sub-micron designs. Excessive switching in test mode causes supply voltage to droop more than in functional mode leading to failures in delay tests that would not occur otherwise under normal operation. Thus, there exists a need to accurately estimate on-chip supply noise early in the design phase to meet power requirements in normal mode and during test to prevent overstimulation during the test cycle and avoid false failures. Simultaneous switching activity (SSA) of several logic components is one of the main sources of power-supply noise (PSN) which results in reduction of supply voltages at the power-supplies of the logic gates. Most existing techniques and tools predict static IR-drop, which accounts for only part of the total voltage drop on the power grid. To our knowledge, inductive drop is not included in current noise analysis for simplification. The power delivery networks in today's very deep-submicron chips are susceptible to slight variations and cause sudden large current spikes leading to higher Ldi 驴 dt than resistive drop essentiating the need to account for this drop. Power-supply noise also impacts circuit operation incurring a significant increase in path delays. However, it is infeasible to carry out full-chip SPICE-level simulations on a design to validate the ATPG generated test patterns. Accurate and efficient techniques are required to quantify supply noise and its impact on path delays to ensure reliable operation in both mission mode and during test. We present a scalable current-based dynamic method to estimate both IR and Ldi / dt drop caused by simultaneous switching activity and use the technique to predict the increase in path delay. Our technique uses simulations of individual extracted paths in comparison to time-consuming full-chip simulations and thus it can be integrated with existing ATPG tools. The method uses these path simulations and a convolution-based technique to estimate power-supply noise and path delays. Simulation results for combinational and sequential benchmark circuits are presented demonstrating the effectiveness of our techniques.