Test strategies for low power devices
Proceedings of the conference on Design, automation and test in Europe
Layout-aware, IR-drop tolerant transition fault pattern generation
Proceedings of the conference on Design, automation and test in Europe
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
A novel faster-than-at-speed transition-delay test method considering IR-drop effects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Emulating and diagnosing IR-drop by using dynamic SDF
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Journal of Electronic Testing: Theory and Applications
Hi-index | 0.00 |
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The supply noise of delay test during at-speed launch and capture is significantly larger compared to normal circuit operation since larger number of transitions occur within a short time frame. Our simulations have shown that for identical switching activity, a pattern with a short switching time frame window will surge more current from the power network, thereby causing higher IR-drop. In this paper, we propose a novel method to measure the average power of at-speed test patterns, referred to as switching cycle average power (SCAP).We present a case study of the IR-drop effects on design performance during at-speed test. A new practical framework is proposed to generate supply noise tolerant delay test patterns. The proposed framework uses existing commercial ATPG tools and a wrapper is added around them. The results demonstrate that the new patterns generated using our framework will significantly reduce the supply noise.