Proceedings of the 20th symposium on Great lakes symposium on VLSI
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
Proceedings of the Conference on Design, Automation and Test in Europe
Emulating and diagnosing IR-drop by using dynamic SDF
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Pseudo-functional testing for small delay defects considering power supply noise effects
Proceedings of the International Conference on Computer-Aided Design
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
Proceedings of the International Conference on Computer-Aided Design
A scalable quantitative measure of IR-drop effects for scan pattern generation
Proceedings of the International Conference on Computer-Aided Design
Journal of Electronic Testing: Theory and Applications
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Journal of Electronic Testing: Theory and Applications
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As technology scales, gate sensitivity to noise increases due to supply voltage scaling and limited scaling of the voltage threshold. As a result, power supply noise plays a greater role in sub-100nm technologies and creates signal integrity issues in the chip. It is vital to consider supply voltage noise effects (i) during design validation to apply sufficient guardbands to critical paths and (ii) during path delay test to ensure the performance and reliability of the chip. In this paper, a novel layout-aware pattern generation procedure for maximizing power supply noise effects on critical paths while considering local voltage drop impacts is proposed. The proposed pattern generation and validation flow is implemented on the ITC’99 b19 benchmark. Experimental results for both wire-bond and flip-chip packaging styles are presented in this paper. Results demonstrate that our proposed method is fast, significantly increases switching around the functionally testable critical paths, and induces large voltage drop on cells placed in the critical paths which results in increased path delay. The proposed method eliminates the very time consuming pattern validation phase that is practiced in industry.