Analysis of performance impact caused by power supply noise in deep submicron devices
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Bounded Adjacent Fill for Low Capture Power Scan Testing
VTS '08 Proceedings of the 26th IEEE VLSI Test Symposium
Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
ATS '09 Proceedings of the 2009 Asian Test Symposium
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
Proceedings of the Conference on Design, Automation and Test in Europe
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Gate delay estimation in STA under dynamic power supply noise
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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Analysis of power grid IR-drop during scan test application has drawn growing attention because excessive IR-drop may cause a functionally correct device to fail at-speed testing. The analysis is challenging since the power grid IR-drop profile depends on not only the switching cells locations but also the power grid structure. This paper presents a scalable implementation methodology for quantifying the IR-drop effects of a set of switching cells. An example of its application to guide power-safe scan pattern generation is illustrated. The scalability and effectiveness of the proposed quantitative measure is evaluated with a 130 nm industrial design with 800 K cells.