Vectorless Analysis of Supply Noise Induced Delay Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Scaling trends of on-chip power distribution noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Timing analysis considering temporal supply voltage fluctuation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Timing-Aware Power-Noise Reduction in Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Worst-case performance prediction under supply voltage and temperature variation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
An RTL-to-GDS2 design methodology for advanced system LSI
Proceedings of the 16th Asia and South Pacific Design Automation Conference
A scalable quantitative measure of IR-drop effects for scan pattern generation
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 2% error on average.