Automatic sizing of power/ground (P/G) networks in VLSI
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Resolving signal correlations for estimating maximum currents in CMOS combinational circuits
DAC '93 Proceedings of the 30th international Design Automation Conference
Vector generation for maximum instantaneous current through supply lines for CMOS circuits
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power estimation tool for sub-micron CMOS VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Current signature compression for IR-drop analysis
Proceedings of the 37th Annual Design Automation Conference
Test Generation for Path Delay Faults Using Binary Decision Diagrams
IEEE Transactions on Computers
Power Bus Maximum Voltage Drop in Digital VLSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A hybrid methodology for switching activities estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing
Proceedings of the 44th annual Design Automation Conference
Transition delay fault test pattern generation considering supply voltage noise in a SOC design
Proceedings of the 44th annual Design Automation Conference
Modeling Power Supply Noise in Delay Testing
IEEE Design & Test
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the Conference on Design, Automation and Test in Europe
NIM: a noise index model to estimate delay discrepancies between silicon and simulation
Proceedings of the Conference on Design, Automation and Test in Europe
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
Journal of Electronic Testing: Theory and Applications
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ATPG tools generate test vectors assuming zero delay model forlogic gates.In reality, however, gates have finite rise and falldelays that are dependent on process, voltage, and temperaturevariations across different dies on a wafer and within a die.A testengineer must verify the vectors for timing correctness before theyare handed off to the product engineer.Currently, validation oftests is done using dynamic simulation of the circuit using the testvectors.A test vector is invalidated if it cannot reliably distinguishbetween a good and a faulty circuit under the signal placement andobservation error window of the tester equipment.Since structuraltests can result in much more switching activity in the circuit thanwhat is estimated during normal functioning, the IR drop in thepower & ground lines can be significant, adversely impacting pathdelays.As a result, the validation performed by simulation can beerror prone.Oversizing the power rails to address this problemimpacts the yield.We therefore propose the verification of testvectors for IR drop failure and present a flow for identifyingfailing vectors.Attempting to address this verification in dynamicsimulation will force the use of circuit simulation or mixed-levelsimulation techniques, which are expensive in terms of run time.We discuss a static approach to validate the test vectors for failurein the presence of IR drop problems.