Combining low-power scan testing and test data compression for system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Inserting Test Points to Control Peak Power During Scan Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Peak-power reduction for multiple-scan circuits during test application
ATS '00 Proceedings of the 9th Asian Test Symposium
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Static Verification of Test Vectors for IR Drop Failure
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
XID: Don't care identification of test patterns for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On systematic illegal state identification for pseudo-functional testing
Proceedings of the 46th Annual Design Automation Conference
Scan power reduction in linear test data compression scheme
Proceedings of the 2009 International Conference on Computer-Aided Design
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects
Proceedings of the Conference on Design, Automation and Test in Europe
A physical-location-aware X-filling method for IR-drop reduction in at-speed scan test
Proceedings of the Conference on Design, Automation and Test in Europe
A physical-location-aware fault redistribution for maximum IR-drop reduction
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A physical-location-aware X-bit redistribution for maximum IR-drop reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IR-drop-induced malfunction is mostly caused by timing violations on activated critical paths during the capture cycle of at-speed scan testing. A critical-path-aware X-filling method is proposed for reducing IR-drop, especially on gates that are close to activated critical paths, thus effectively preventing test-induced yield loss.