HOPE: an efficient parallel fault simulator for synchronous sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Test vector encoding using partial LFSR reseeding
Proceedings of the IEEE International Test Conference 2001
Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Computers
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
ITC '04 Proceedings of the International Test Conference on International Test Conference
Survey of Test Vector Compression Techniques
IEEE Design & Test
Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing
Proceedings of the 44th annual Design Automation Conference
Scan chain clustering for test power reduction
Proceedings of the 45th annual Design Automation Conference
On capture power-aware test data compression for scan-based testing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan power reduction for linear test compression schemes through seed selection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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XOR network-based on-chip test compression schemes have been widely employed in large industrial scan designs due to their high compression ratio and efficient decompression mechanism. Nevertheless, such a scheme necessitates high unspecified bit ratios in the original test cubes, resulting in quite significant difficulties in preprocessing test cubes for scan power reduction. The linear mapping from the original cubes to the compressed seeds typically provides extra degrees of flexibility as multiple seeds may reconstruct the test cube. Appreciable power reductions in the decompressed test data can be attained through the pinpointing of the power-optimal seeds during the compression phase. The proposed work explores the aforementioned flexibility in the seed space, and proposes the mathematical and algorithmic framework for a power-aware linear test compression scheme. The proposed technique incurs no hardware overhead over the traditional linear compression scheme; it can be easily embedded furthermore into the industrial test compaction/compression flow. Experimental results confirm that the proposed technique delivers significant scan power reduction with negligible impact on the compression ratio.