Scan Power Minimization through Stimulus and Response Transformations
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Simultaneous Reduction of Dynamic and Static Power in Scan Structures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A critical-path-aware partial gating approach for test power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing
Proceedings of the 44th annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells
Journal of Electronic Testing: Theory and Applications
Efficient partial scan cell gating for low-power scan-based testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Dynamic scan chain partitioning for reducing peak shift power during test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
On reducing scan shift activity at RTL
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
This paper presents a procedure for inserting test points at the outputs of scan elements of afull-scan circuit in such a manner that the peak power during scan testing is kept below a specified limit while maintaining the original fault coverage. If the power in a clock cycle during scan testing exceeds a specified limit (which depends on the peak power the chip has been designed to supply), a "peak power violation" is said to occur. Given a set of vectors, simulation is used to identify the cycles in which peak power violations occur (called "violating cycles"). For each violating cycle, the reduction in power caused by a control-0 and control-1 test point at each scan element is determined by simulation. The optimization problem then is to select as few test points as possible to eliminate all violating cycles. We present a heuristic procedure for minimizing the number of test points using integer linear programming techniques. The test points are activated and deactivated in a manner such that there is neither any loss in fault coverage nor peak power violations in the capture cycle. Experimental results indicate that the proposed procedure is very effective in controlling peak power during scan testing using a small number of test points.