IEEE Transactions on Computers - Special issue on fault-tolerant computing
Acceleration techniques for dynamic vector compaction
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Test Data Decompression for Multiple Scan Designs with Boundary Scan
IEEE Transactions on Computers
Skewed-Load Transition Test: Part 1, Calculus
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
Test vector decompression via cyclical scan chains and its application to testing core-based designs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Inserting Test Points to Control Peak Power During Scan Testing
DFT '02 Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A novel scan architecture for power-efficient, rapid test
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Reducing Test Application Time for Full Scan Embedded Cores
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Scan Vector Compression/Decompression Using Statistical Coding
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Test Data Compression for System-on-a-Chip Using Golomb Codes
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
ITC '02 Proceedings of the 2002 IEEE International Test Conference
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs
Proceedings of the conference on Design, automation and test in Europe
Test Vector Modification for Power Reduction during Scan Testing
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing of Digital Systems
Test-decompression mechanism using a variable-length multiple-polynomial LFSR
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Evolutionary Optimization in Code-Based Test Compression
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Nine-coded compression technique for testing embedded cores in socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan testing for test data compression using a routing-driven scan architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.