An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs

Authors:
A. Pandey;J. Patel
Affiliations:
Advanced Micro Devices, Inc., Sunnyvale, CA.;Center for Reliable & High-Performance Computing, 1308 W Main Street, University of Illinois, Urbana, IL
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2002

Citing 0
Cited 10

A cocktail approach on random access scan toward low power and high efficiency test

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A multilayer data copy test data compression scheme for reducing shifting-in power for multiple scan design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A selective pattern-compression scheme for power and test-data reduction

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment

Journal of Electronic Testing: Theory and Applications
Low power Illinois scan architecture for simultaneous power and test data volume reduction

Proceedings of the conference on Design, automation and test in Europe
A Test Data Compression Scheme for Reducing Power Based on OLELC and NBET

ICIC '08 Proceedings of the 4th international conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications - with Aspects of Theoretical and Methodological Issues
Study on Test Data Reduction Combining Illinois Scan and Bit Flipping

IEICE - Transactions on Information and Systems
Scalable adaptive scan (SAS)

Proceedings of the Conference on Design, Automation and Test in Europe
On reducing test power and test volume by selective pattern compression schemes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Test data compression using interval broadcast scan for embedded cores

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

As the complexity of VLSI circuits is increasing due to theexponential rise in transistor count per chip, testing cost isbecoming an important factor in the overall integrated circuit(IC) manufacturing cost. This paper addresses the issueof decreasing test cost by lowering the test data bits andthe number of clock cycles required to test a chip. We proposea new incremental algorithm for generating tests forIllinois Scan Architecture (ILS) based designs and provideanalysis of test data and test time reduction. This algorithmis very efficient in generating tests for a number of ILS designsin order to find the most optimal configuration.