Test volume and application time reduction through scan chain concealment
Proceedings of the 38th annual Design Automation Conference
Extending OPMISR beyond 10x Scan Test Efficiency
IEEE Design & Test
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs
Proceedings of the conference on Design, automation and test in Europe
Reducing Test Application Time Through Test Data Mutation Encoding
Proceedings of the conference on Design, automation and test in Europe
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Relating Entropy Theory to Test Data Compression
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Test data compression technique for embedded cores using virtual scan chains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A cocktail approach on random access scan toward low power and high efficiency test
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
System-on-a-chip test-data compression and decompression architectures based on Golomb codes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Variable-length input Huffman coding for system-on-a-chip test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient test vector compression scheme using selective Huffman coding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A new test data compression scheme is introduced. This scheme encodes the test data provided by the core vendor, using a new and very effective compression scheme based on OLEL coding and neighboring bit-wise exclusive-or transform(OCNBET). Codeword is divided into two parts according to the position: odd bits and even bits. The odd bits of codeword are used to represent the length of runs and the even bits of codeword are used to represent whether a run is finished. Furthermore, a neighboring bit-wise exclusive-or transform is introduced to increase the probability of runs of 0s in the transformed data, so significant compression improvements and power efficient compared with the already known schemes are achieved. A simple architecture is proposed for decoding the compressed data on chip. Its hardware overhead is very low and comparable to that of the most efficient methods in the literature. Experimental results for the six largest ISCAS-89 benchmark circuits show that the proposed scheme is obviously better than the already known schemes in the aspects of compression ratio, power and the decompression structure.