Test application time and volume compression through seed overlapping
Proceedings of the 40th annual Design Automation Conference
CircularScan: A Scan Architecture for Test Cost Reduction
Proceedings of the conference on Design, automation and test in Europe - Volume 2
3-Stage Variable Length Continuous-Flow Scan Vector Decompression Scheme
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Using MUXs Network to Hide Bunches of Scan Chains
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
XPAND: An Efficient Test Stimulus Compression Technique
IEEE Transactions on Computers
Frugal linear network-based test decompression for drastic test cost reductions
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
A Test Data Compression Scheme for Reducing Power Based on OLELC and NBET
ICIC '08 Proceedings of the 4th international conference on Intelligent Computing: Advanced Intelligent Computing Theories and Applications - with Aspects of Theoretical and Methodological Issues
Improving linear test data compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scan cell positioning for boosting the compression of fan-out networks
Journal of Computer Science and Technology - Special section on trust and reputation management in future computing systmes and applications
Test data compression using selective encoding of scan slices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
COMPAS – compressed test pattern sequencer for scan based circuits
EDCC'05 Proceedings of the 5th European conference on Dependable Computing
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Journal of Electronic Testing: Theory and Applications
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A methodology for the determination of decompressionhardware that guarantees complete fault coverage for a unifiedcompaction/compression scheme is proposed. Test cubeinformation is utilized for the determination of a near optimaldecompression hardware. The proposed scheme attainssimultaneously high compression levels and reducedpattern counts through a linear decompression hardware.Significant test volume and test application time reductionsare delivered through the scheme we propose while a highlycost effective hardware implementation is retained.