A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Authors:
N. Badereddine;Z. Wang;P. Girard;K. Chakrabarty;A. Virazel;S. Pravossoudovitch;C. Landrault
Affiliations:
Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université de Montpellier II/CNRS, Montpellier Cedex 5, France 34392;Department of Electrical and Computer Engineering, Duke University, Durham, USA 27708;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université de Montpellier II/CNRS, Montpellier Cedex 5, France 34392;Department of Electrical and Computer Engineering, Duke University, Durham, USA 27708;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université de Montpellier II/CNRS, Montpellier Cedex 5, France 34392;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université de Montpellier II/CNRS, Montpellier Cedex 5, France 34392;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, Université de Montpellier II/CNRS, Montpellier Cedex 5, France 34392
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2008

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Abstract

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 14脳 reduction in test data volume and 98% test power reduction can be obtained simultaneously.