Rapid Generation of Thermal-Safe Test Schedules
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Minimizing test power in SRAM through reduction of pre-charge activity
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing: Theory and Applications
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests
Proceedings of the conference on Design, automation and test in Europe
Variation-Tolerant, Power-Safe Pattern Generation
IEEE Design & Test
On reducing both shift and capture power for scan-based testing
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
Proceedings of the conference on Design, automation and test in Europe
On capture power-aware test data compression for scan-based testing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A power-effective scan architecture using scan flip-flops clustering and post-generation filling
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Dynamic scan chain partitioning for reducing peak shift power during test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan testing for test data compression using a routing-driven scan architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Low-power scan operation in test compression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
QC-fill: quick-and-cool X-filling for multicasting-based scan test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
On reducing scan shift activity at RTL
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automated data analysis solutions to silicon debug
Proceedings of the Conference on Design, Automation and Test in Europe
QC-fill: an X-fill method for quick-and-cool scan test
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved weight assignment for logic switching activity during at-speed test pattern generation
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Capture-power-aware test data compression using selective encoding
Integration, the VLSI Journal
A new scheme of test data compression based on equal-run-length coding (ERLC)
Integration, the VLSI Journal
MVP: capture-power reduction with minimum-violations partitioning for delay testing
Proceedings of the International Conference on Computer-Aided Design
Controlling peak power consumption during scan testing: power-aware DfT and test set perspectives
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Automating data analysis and acquisition setup in a silicon debug environment
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-safe application of tdf patterns to flip-chip designs during wafer test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power skewed-load tests based on functional broadside tests
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Design-for-testability for multi-cycle broadside tests by holding of state variables
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power test sets under test-related primary input constraints
International Journal of Critical Computer-Based Systems
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Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum-transition don't care fill, special scan cells, and scan chain partitioning), limited work has been carried out toward reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex automatic test pattern generation (ATPG) algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture-power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2%-3%). An algorithmic procedure for assigning flip-flops to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak-power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and, respectively, maximum number of simultaneous transitions.