Minimizing test power in SRAM through reduction of pre-charge activity

Authors:
Luigi Dilillo;Paul Rosinger;Bashir M. Al-Hashimi;Patrick Girard
Affiliations:
University of Southampton, Southampton, United Kingdom;University of Southampton, Southampton, United Kingdom;University of Southampton, Southampton, United Kingdom;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, -- LIRMM, France
Venue:
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Year:
2006

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Abstract

In this paper we analyze the test power of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test mode because of the predictable addressing sequence. We exploit this observation in order to minimize power dissipation during test by eliminating the unnecessary power consumption associated with the pre-charge activity. This is achieved through a modified pre-charge control circuitry, exploiting the first degree of freedom of March tests, which allows choosing a specific addressing sequence. The efficiency of the proposed solution is validated through extensive Spice simulations.