A Gated Clock Scheme for Low Power Testing of Logic Cores

Authors:
Yannick Bonhomme;Patrick Girard;Loïs Guiller;Christian Landrault;Serge Pravossoudovitch;Arnaud Virazel
Affiliations:
Aff1 Aff2;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, UMR 5506/Université Montpellier II / CNRS, Montpellier Cedex 05, France 34392;Aff1 Aff3;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, UMR 5506/Université Montpellier II / CNRS, Montpellier Cedex 05, France 34392;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, UMR 5506/Université Montpellier II / CNRS, Montpellier Cedex 05, France 34392;Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier, UMR 5506/Université Montpellier II / CNRS, Montpellier Cedex 05, France 34392
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2006

Citing 24
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Abstract

Test power is now a big concern in large core-based systems. In this paper, we present a general approach for minimizing power consumption during test of integrated circuits or embedded cores. The proposed low power/energy technique is based on a gated clock scheme that can be used in a test-per-scan or a test-per-clock environment. The idea is to reduce the clock rate on the scan path (test-per-scan) or the test pattern generator (test-per-clock) without increasing the test time. Numerous advantages can be found in applying such a technique.