POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing

Low Power BIST by Filtering Non-Detecting Vectors

Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999

Survey of Low-Power Testing of VLSI Circuits

IEEE Design & Test

Genetic Algorithm based Approach for Low Power Combinational Circuit Testing

VLSID '03 Proceedings of the 16th International Conference on VLSI Design

Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Power Reduction in Test-Per-Scan BIST

IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)

Low Power Testing of VLSI Circuits: Problems and Solutions

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

Peak Power Reduction in Low Power BIST

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design

A Gated Clock Scheme for Low Power Testing of Logic Cores

Journal of Electronic Testing: Theory and Applications

System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability

Suitability of various low-power testing techniques for IP core-based SoC: a survey

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions

Test patterns of multiple SIC vectors: theory and application in BIST schemes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems