Low power design in deep submicron electronics
Low power design in deep submicron electronics
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Testability Trade-Offs for BIST Data Paths
Journal of Electronic Testing: Theory and Applications
Scan test planning for power reduction
Proceedings of the 44th annual Design Automation Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test patterns of multiple SIC vectors: theory and application in BIST schemes
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, two techniques to reduce the energyand the average power consumption of the system are proposed. Theyare based on the fact that as the test progresses, the detectionefficiency of the pseudo-random vectors decreases very quickly. Manyof the pseudo-random vectors will not detect faults in spite ofconsuming a significant amount of energy from the power supply. Inorder to prevent this energy consumption, a filtering of thenon-detecting vectors and a reseeding strategy are proposed.These techniques are evaluated on the set of ISCAS-85 benchmarkcircuits. Extensive simulations have been made using the SAIL energysimulator showing that, in large circuits, the energy consumption and theaverage power savings reach 90.0% with a mean value of 74.2% with the filtering technique, and 97.2% with an average value of 90.9% with the reseeding strategy.