Integration, the VLSI Journal - Special issue on VLSI testing
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
ATS '99 Proceedings of the 8th Asian Test Symposium
Low Power BIST by Filtering Non-Detecting Vectors
ETW '99 Proceedings of the 1999 IEEE European Test Workshop
Test Power: a Big Issue in Large SOC Designs
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Low-Energy BIST Design for Scan-based Logic Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Low Power BIST via Non-Linear Hybrid Cellular Automata
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Jump Scan: A DFT Technique for Low Power Testing
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
Partial Gating Optimization for Power Reduction During Test Application
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
A BIST TPG for low power dissipation and high fault coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-Transition Test Pattern Generation for BIST-Based Applications
IEEE Transactions on Computers
Test strategies for low power devices
Proceedings of the conference on Design, automation and test in Europe
A new low power test pattern generator using a variable-length ring counter
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Efficient Don't Care Filling for Power Reduction during Testing
ARTCOM '09 Proceedings of the 2009 International Conference on Advances in Recent Technologies in Communication and Computing
Sequential circuit ATPG using combinational algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Test power is the major issue for current generation VLSI testing. It has become the biggest concern for today's SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.