Suitability of various low-power testing techniques for IP core-based SoC: a survey
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
A modified scheme for simultaneous reduction of test data volume and testing power
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Hi-index | 0.00 |
Power consumption during test mode is much higher than in normal mode of operation. This paper addresses issue of assigning suitable values to the unspecified bits (don’t care) in the test patterns so that both static and dynamic power consumption during testing is reduced. We have used a Genetic Algorithm based heuristic to fill the don’t cares. Our approach produces an average percentage improvement of 31.9, 37.0, and 37.7 in dynamic power and 3.0, 7.4, and 5.3 leakage power over 0-fill, 1-fill, and MT-fill algorithms for don’t care filling, considering the test patterns having unspecified bits in ISCAS’89 benchmark suite.