Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-chip test generation for combinational circuits by LFSR modification
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
Low Power/Energy BIST Scheme for Datapaths
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Static Compaction Techniques to Control Scan Vector Power Dissipation
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power scan testing and test data compression for system-on-a-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient scan-based BIST scheme for low power testing of VLSI chips
Proceedings of the 2006 international symposium on Low power electronics and design
A new low energy BIST using a statistical code
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Suitability of various low-power testing techniques for IP core-based SoC: a survey
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
Virtual scan chains reordering using a RAM-based module for high test compression
Microelectronics Journal
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In a random testing environment, a significant amount ofenergy is wasted in the LFSR and in the CUT by uselesspatterns that do not contribute to fault dropping. Anothermajor source of energy drainage is the loss due to randomswitching activity in the CUT and in the scan path betweenapplications of two successive vectors. In this work, a newbuilt-in self-test (BIST) scheme for scan-based circuits isproposed for reducing such energy consumption. Amapping logic is designed which modifies the statetransitions of the LFSR such that only the useful vectorsare generated according to a desired sequence. Further, itreduces test application time without affecting faultcoverage. Experimental results on ISCAS-89 benchmarkcircuits reveal a significant amount of energy savings inthe LFSR during random testing.