Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
Shift Register Sequences
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
Journal of Electronic Testing: Theory and Applications
Power-/Energy Efficient BIST Schemes for Processor Data Paths
IEEE Design & Test
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Low-Energy BIST Design for Scan-based Logic Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Analysis of Powe Reduction Techniques in Scan Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Power Reduction in Test-Per-Scan BIST
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
A Queueing System with Inverse Discipline, Two Types of Customers, and Markov Input Flow
Automation and Remote Control
Low-power weighted pseudo-random BIST using special scan cells
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Scan-BIST based on transition probabilities
Proceedings of the 41st annual Design Automation Conference
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
Journal of Electronic Testing: Theory and Applications
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing: Theory and Applications
Efficient scan-based BIST scheme for low power testing of VLSI chips
Proceedings of the 2006 international symposium on Low power electronics and design
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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A new BIST TPG design, called low-transition random TPG (LT-RTPG), that is comprised of an LFSR,a k-input AND gate, and a T flip-flop, is presented.When used to generate test patterns for test-per-scanBIST, it decreases the number of transitions that occur during scan shifting and hence decreases the heatdissipated during testing. Various properties of LT-RTPG's are studied and a methodology for their designis presented. Experimental results demonstrate thatLT-RTPG's designed using the proposed methodologydecrease the heat dissipated during BIST by significantamounts while attaining high fault coverage, especiallyfor circuits with moderate to large number of scan inputs.