Scheduling tests for VLSI systems under power constraints
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A method of delay fault test generation
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption
ATS '99 Proceedings of the 8th Asian Test Symposium
An Input Control Technique for Power Reduction in Scan Circuits During Test Application
ATS '99 Proceedings of the 8th Asian Test Symposium
A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
A Test Vector Inhibiting Technique for Low Energy BIST Design
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Addressable Test Ports An Approach to Testing Embedded Cores
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Broadcasting test patterns to multiple circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is developed which can significantly reduce the peak power. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed.