Journal of Electronic Testing: Theory and Applications
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Token Scan Architecture for Low Power Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Reducing Average and Peak Test Power Through Scan Chain Modification
Journal of Electronic Testing: Theory and Applications
Scan Power Minimization through Stimulus and Response Transformations
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
X-filling for simultaneous shift- and capture-power reduction in at-speed scan-based testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposes a novel technique to minimize the switching activity of full-scan circuits during test application. The basic idea is to identify an input control pattern for a full-scan circuit such that by applying the pattern to the primary inputs of the circuit during the scan operation, the switching activity in the combinational part can be minimized or even eliminated. A D-algorithm-like pattern generator is developed to generate the control pattern. This input control technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show that the vector ordering and the latch ordering techniques can achieve about 19.29% of average improvement, while 29.28% average improvement can be achieved if the input control technique is employed before the vector ordering and latch ordering techniques.