ATPG for Heat Dissipation Minimization During Test Application
IEEE Transactions on Computers
An Input Control Technique for Power Reduction in Scan Circuits During Test Application
ATS '99 Proceedings of the 8th Asian Test Symposium
Adapting Scan Architectures for Low Power Operation
ITC '00 Proceedings of the 2000 IEEE International Test Conference
A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores
ATS '01 Proceedings of the 10th Asian Test Symposium
A Modified Clock Scheme for a Low Power BIST Test Pattern Generator
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Test Power Reduction through Minimization of Scan Chain Transitions
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Minimized Power Consumption For Scan-Based Bist
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scan Power Minimization through Stimulus and Response Transformations
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Fast and energy-frugal deterministic test through efficient compression and compaction techniques
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
Journal of Electronic Testing: Theory and Applications
Dynamic scan chain partitioning for reducing peak shift power during test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
Journal of Electronic Testing: Theory and Applications
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.