Transition density, a stochastic measure of activity in digital circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
On average power dissipation and random pattern testability of CMOS combinational logic networks
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
ATPG for heat dissipation minimization during scan testing
DAC '97 Proceedings of the 34th annual Design Automation Conference
ATPG for Heat Dissipation Minimization During Test Application
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
IEEE Transactions on Computers
Energy Saving Testing of Circuits
Automation and Remote Control
Journal of Electronic Testing: Theory and Applications
Survey of Low-Power Testing of VLSI Circuits
IEEE Design & Test
Genetic Algorithm based Approach for Low Power Combinational Circuit Testing
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Token Scan Architecture for Low Power Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Low Power Testing of VLSI Circuits: Problems and Solutions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Design of Routing-Constrained Low Power Scan Chains
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power-Driven Routing-Constrained Scan Chain Design
Journal of Electronic Testing: Theory and Applications
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A Gated Clock Scheme for Low Power Testing of Logic Cores
Journal of Electronic Testing: Theory and Applications
Critical-path-aware X-filling for effective IR-drop reduction in at-speed scan testing
Proceedings of the 44th annual Design Automation Conference
Search space pruning techniques in ATPG for VLSI circuits
ICC'05 Proceedings of the 9th International Conference on Circuits
Low-power multi-core ATPG to target concurrency
Integration, the VLSI Journal
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing
Journal of Electronic Testing: Theory and Applications
Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
LPTest: a Flexible Low-Power Test Pattern Generator
Journal of Electronic Testing: Theory and Applications
Power supply noise reduction for at-speed scan testing in linear-decompression environment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On reducing scan shift activity at RTL
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the test pattern generation phase and selects a subset of sequences able to reduce the consumed power, without reducing the fault coverage. The method is composed of three independent steps: redundant test pattern generation, power consumption measurement, optimal test sequence selection. The experimental results gathered on the ISCAS benchmark circuits show that our approach decreases on average the power consumption by 70% with respect to the original test pattern, generated ignoring the heat dissipation problem.