Introduction to algorithms
Two-level logic minimization: an overview
Integration, the VLSI Journal
Solving covering problems using LPR-based lower bounds
DAC '97 Proceedings of the 34th annual Design Automation Conference
New Static Compaction Techniques of Test Sequences for Sequential Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Negative thinking in branch-and-bound: the case of unate covering
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accelerating the compaction of test sequences in sequential circuits through problem size reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a, common, unified approach to solve either the test sequence compaction problem or the power minimization problem during circuit testing. This approach is based on an exact Branch and Bound algorithm that exploits information from the respective problems. In particular decision making during the Branch and Bound method follows some rules devised so as to avoid unnecessary choices and thus reducing the search space. Experimental results that are presented, comparing the proposed algorithm with other solvers from literature, show the effectiveness of the proposed method.