Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Data Structures and Algorithms
Data Structures and Algorithms
A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Constraint Driven Pin Mapping for Concurrent SOC Testing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Compact ATPG for Concurrent SOC Testing
MTV '04 Proceedings of the Fifth International Workshop on Microprocessor Test and Verification
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
IEEE Transactions on Computers
Efficient identification of (critical) testable path delay faults using decision diagrams
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test pattern generation using Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A function-based automatic test pattern generation (ATPG) tool for embedded core testing is presented that reduces test cost and considers test power dissipation of system-on-chip (SoC). Cores are tested concurrently with the use of test functions, as opposed to simple patterns, and by I/O pin allocation on the test access mechanism (TAM) during a compact ATPG process. Turnaround time benefits from pre-existing test vectors, or test functions supplied by the provider of each core. The presented method also targets low-power dissipation by considering the switching activity on the SoC inputs. Experimental results show a significant reduction in the test application time due to the achieved level of concurrency.