Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets

Authors:
Yu Huang;Wu-Tung Cheng;Chien-Chung Tsai;Nilanjan Mukherjee;Sudhakar M. Reddy
Affiliations:
-;-;-;-;-
Venue:
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Year:
2003

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Abstract

An algorithm for mapping coreterminals to System-On-a-Chip (SOC) I/O pinsand scheduling tests in order to achieve cost-efficientconcurrent test for core-based designs ispresented in this paper. In this work "static" pinmapping and test scheduling for concurrenttesting are studied for the case of multiple testsets for each core. The problem is formulated asa constrained two-dimensional bin-packingproblem. A heuristic algorithm is then proposedto determine a solution. The objectives drivingthis solution are geared towards reducing thetotal test application time of SOC and satisfyingthe test constraints such as limited number ofSOC pins and maximum peak power dissipationspecified by core integrators. Experimentalresults demonstrate the effectiveness of theproposed method.