Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Data Structures and Algorithms
Data Structures and Algorithms
A Unifying Methodology for Intellectual Property and Custom Logic Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing embedded-core based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Test wrapper and test access mechanism co-optimization for system-on-chip
Proceedings of the IEEE International Test Conference 2001
Constraint Driven Pin Mapping for Concurrent SOC Testing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
20.3 A Test Pattern Generation Methodology for Low-Power Consumption
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D
ATS '01 Proceedings of the 10th Asian Test Symposium
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test set compaction algorithms for combinational circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A functional Automatic Test Pattern Generation (ATPG) for embedded core testing is presented that meets power constraints requirements and time to market consideration. Quick turnaround time for the ATPG is obtained by utilizing compact sets of test vectors. Use of test functions for the embedded cores control the switching activity so that the generated test vectors meet constraints on power dissipation. Concurrency is guaranteed with the use of test functions (as opposed to patterns) and appropriate I/O pin TAM allocation during a compact ATPG process that benefits from pre-existing test vectors. Low power dissipation is also facilitated by test functions and is driven by a metric that requires that a very small portion of each core net-list is available.